Abstract

In the last decades, finite control set-model predictive control (FCS-MPC) has been extensively investigated. This control strategy uses the system model to determine the optimal input that minimizes a predefined cost function. This procedure is performed by evaluating the admissible inputs of the converter model. In order to achieve a proper performance of the control strategy, a small sampling time must be used. In practice, the computational effort and processing time are critical factors that depend directly on the number of admissible states of the topology. With the objective of reducing the execution time needed by the algorithm, it is possible to take advantage of the high degree of parallelism that can be obtained from a field-programmable gate array (FPGA). This paper deals with the implementation of FCS-MPC in an FPGA XC3S3500E to control a power cell of a cascaded half bridge (CHB) converter. The design is divided into subparts, called modules, which can be projected to control multiple cells using only one chip. In addition, with the aim to restrict the use of hardware to the available resources, the document presents a series of considerations related to the algorithm and its implementation. This paper presents a detailed guide with emphasis on the design and outlining of each module in order to reduce the developing times for researchers in the area of power converters.