Abstract

We have built a 16-tap, 7-bit, 200MHz, mixed-signal FIR filter that consumes 3mW at 3.3V. The filter uses p-channel synapse transistors to store the tap coefficients; electron tunneling and hot-electron injection to modify the tap weights; digital registers for the delay line; and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap weights. The measured bandwidth is 225MHz; the measured tap multiplier resolution is 7 bits at 200MHz. The total die area is 0.13mm(2) we can readily scale the design to higher bit resolutions and longer delay-lines.