A hardware accelerator for entropy estimation using the top-k most frequent elements
Abstract
Estimating the empirical entropy of the elements in a dataset is an important task in data analysis. In particular, empirical entropy can be effectively used to detect anomalies in network traffic. However, computing the empirical entropy of a large dataset is computationally expensive and requires a large amount of memory. This is particularly important in high-speed network traffic analysis, where computing the entropy of a data flow in real time requires using hardware accelerators with restricted on-chip memory and arithmetic resources. In this work, we propose a method to estimate the entropy using a streaming algorithm with sublinear space requirements. Our approach uses a sketch to estimate the frequency of the elements in the stream, and a priority queue to store the top-k most frequent elements. We show that our method can provide a good approximation of the entropy of the dataset, and present the design of a hardware accelerator that can compute the entropy of the stream with a throughput of one packet per clock cycle. Implemented on a Xilinx Zynq UltraScale + MPSoC ZCU102 FPGA, our accelerator can operate at line rates above 181 Gbps, consuming 511 mW and using less than 24% of the resources available on the device.
Más información
| Título según SCOPUS: | A hardware accelerator for entropy estimation using the top-k most frequent elements |
| Título de la Revista: | Proceedings - Euromicro Conference on Digital System Design, DSD 2020 |
| Editorial: | Institute of Electrical and Electronics Engineers Inc. |
| Fecha de publicación: | 2020 |
| Año de Inicio/Término: | August 26 - 28, 2020 |
| Página final: | 148 |
| Idioma: | English |
| URL: | http://dx.doi.org/10.1109/DSD51259.2020.00032 |
| DOI: |
10.1109/DSD51259.2020.00032 |
| Notas: | SCOPUS |