Abstract

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-mu m CMOS technology whereby the effective area of 1 mu m(2) single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr0.8Bi2.2Ta2O9 (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81 mu m(2) three-dimensional (3-D) capacitors (2Pr similar to 15 mu C/cm(2)) than for 1000 mu m(2) 2-D capacitors (2Pr similar to 10 mu C/cm(2)). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10(11) cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85 degrees C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.