A streaming algorithm and hardware accelerator for top-K flow detection in network traffic
Keywords: field, programmable gate array; hardware acceleration; network measurement; sketch, based algorithms; Top, K estimation
Abstract
Identifying the largest K flows in network traffic is an important task for applications such as flow scheduling and anomaly detection, which aim to improve network efficiency and security. However, accurately estimating flow frequencies is challenging due to the large number of flows and increasing network speeds. Hardware accelerators are often used in this endeavor due to their high computational power, but their limited amount of on-chip memory constrains their performance. Various sketch-based algorithms have been proposed to estimate properties of traffic such as frequency, with lower memory usage and theoretical bounds, but they often under perform with the skewed distribution of network traffic. In this work, we propose an algorithm for top- K identification using a modified TowerSketch and a priority queue array. Tested on real traffic traces, we identify the top- K flows, with K up to 32,768, with a precision of more than 0.94, and estimate their frequency with an average relative error under 1.96%. We designed and implemented an accelerator for this algorithm on an AMD Virtex U280 UltraScale+ FPGA, which processes one packet per cycle at 392 MHz, reaching a minimum line rate of more than 200 Gbps. © 2025 IEEE.
Más información
| Título según WOS: | ID WOS:001717790400010 Not found in local WOS DB |
| Título de la Revista: | Proceedings - 2025 28th Euromicro Conference on Digital System Design, DSD 2025 |
| Editorial: | Institute of Electrical and Electronics Engineers Inc. |
| Fecha de publicación: | 2025 |
| Página de inicio: | 73 |
| Página final: | 80 |
| Idioma: | English |
| DOI: |
10.1109/DSD67783.2025.00022 |
| Notas: | ISI |