Fundamental Circuit Topology of Duo-Active- Neutral-Point-Clamped, Duo-Neutral-Point-Clamped, and Duo-Neutral-Point-Piloted Multilevel Converters

Dargahi, V; Abarzadeh, M; Corzine, KA; Enslin, JH; Sadigh, AK; Rodriguez, J; Blaabjerg, F; Maqsood, A

Keywords: Diode abatement, duo-active-neutral-point-clamped (D-ANPC) converter, duo-neutral-point-clamped (D-NPC) converter, duo-neutral-point-piloted (D-NPP) converter, flying-capacitor (FC) energy reduction, FC voltage decrease, insulated-gate bipolar transistor (IGBT) abatement

Abstract

Multilevel voltage-source converters are well-suited for power conversion applications demanding higher power density, reliability, efficiency, and power quality. An unremitting and persistent research for developing advanced multilevel converter topologies with improved characteristics, performance, modulation techniques, and control methods continues. This paper proposes duo-neutral-point-clamped (D-NPC), duo-activeneutral-point-clamped (D-ANPC), and duo-neutral-point-piloted (D-NPP) multilevel voltage-sourced converter topologies. The D-NPC, D-ANPC, and D-NPP converters phase-leg is realized by adding low-frequency semiconductor power switches to their structures. This results in a substantial reduction in the number of the high-frequency pulsewidth-modulation insulated-gate bipolar transistors and clamping passive devices including diodes as well as flying-capacitors (FCs). Moreover, a drastic abatement in the total voltage rating and total stored energy of the FCs within the D-ANPC topology is achieved compared to the classic ANPC configuration. The experimental results are provided for D-NPC, D-ANPC, and D-NPP converters to validate the feasibility of their topology and modulation method for control of the multilevel converters.

Más información

Título según WOS: Fundamental Circuit Topology of Duo-Active- Neutral-Point-Clamped, Duo-Neutral-Point-Clamped, and Duo-Neutral-Point-Piloted Multilevel Converters
Título de la Revista: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volumen: 7
Número: 2
Editorial: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Fecha de publicación: 2019
Página de inicio: 1224
Página final: 1242
Idioma: English
DOI:

10.1109/JESTPE.2018.2859313

Notas: ISI