Physical design of FPGA interconnect to prevent information leakage
Abstract
In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.
Más información
| Título según WOS: | ID WOS:000254855700008 Not found in local WOS DB |
| Título de la Revista: | PROGRESS IN ARTIFICIAL INTELLIGENCE AND PATTERN RECOGNITION, IWAIPR 2018 |
| Volumen: | 4943 |
| Editorial: | SPRINGER INTERNATIONAL PUBLISHING AG |
| Fecha de publicación: | 2008 |
| Página de inicio: | 87 |
| Página final: | + |
| DOI: |
10.1007/978-3-540-78610-8_11 |
| Notas: | ISI |