Abstract

In this paper, an in-depth timing analysis of asynchronous bundled-data circuits is presented. We leverage the controller Signal Transition Graph to extract and classify their relative timing constraints. Thanks to the Local Clock Set methodology, we show how to define generic rules to translate these constraints into SDC commands for standard EDA tools. As examples, three 2-phase protocols and four 4-phase protocols are analyzed, covering both flip-flop-based and latch-based designs. Additionally, this methodology has been applied to define the timing constraints of reactive clock circuits. Moreover, the method is beneficial for comparing the different bundled-data circuit implementations in terms of timing constraints complexity and timing analysis execution time.