Abstract

While the von Neumann architecture played a leading role in CMOS-based computing systems for several decades, nowadays in-memory computing is an alternative approach being pursued, with resistive switching devices (memristors) in crossbar arrays considered as the enabling technology. In this context, this paper provides a practical solution for a viable in-memory computing architecture within the reach of today ' s technology, through a variability-tolerant ReRAM-based ratioed combinational logic design scheme, inspired on the pseudo-NMOS logic design. The reason we focus on this scheme is because it is simple, crossbar-compatible, completely tolerant to variability, compatible with either filamentary or interfacial switching type devices, and it does not affect the memristor endurance. We highlight all the important characteristics and advantages offered by this scheme, compared to other stateful logic schemes based on memristors, such as IMPLY and MAGIC. We conclude this paper presenting SPICE-based circuit simulation results concerning a 1-bit full adder implementation and show that our proposed ratioed logic design outperforms the rest in terms of speed and area requirements.