Abstract

Resistive RAM (ReRAM) technology is nowadays highly considered for the development of future computational memories. So far, several works have demonstrated logic gates which use data stored in the state of the resistive switching devices (memristors) as logic input/output. However, requirements of topological nature, such as crossbar array-compatibility and word-wise memory operation, along with the impact of device nonidealities, have not always been considered. Therefore, in this work we present some key design considerations, contributing towards the development of a ReRAM-based computational memory. We comment on proper logic design styles which are independent of memristor device technology features and tolerant to variability. Finally, we present a segmented 1T1R ReRAM architecture which has functional features that benefit latency and flexibility of data movement, required for multi-level (sequential) in-memory logic computations and also arithmetic operations.