Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM
Abstract
Resistive RAM (ReRAM) technology is continuously maturing and it is attracting important investments towards more energy-efficient computing systems. Recent approaches to ReRAM-based computing consider the in-memory computations equivalent to memory read operations. In this context, here we summarize a nonstateful ratioed logic style and guide the reader through the design of a computational 1T1R ReRAM module supporting reliable, variability-tolerant, and device technology-independent in-memory logic operations. We present circuit simulations of a 1-bit Full Adder to validate the robustness of the multi-level ratioed logic computations. Moreover, we underline the advantageous performance of nonstateful ratioed logic compared to stateful logic alternatives. Through a common ground basis used to simplify comparisons by translating computing steps/cycles into memory read/write operations, we found promising results in terms of delay and energy consumption compared to performance of stateful logic counterparts. Such results highlight the important benefits gained by basing all in-memory logic computations on memory read operations instead of conditional write operations.
Más información
Título según WOS: | Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM |
Título de la Revista: | PROCEEDINGS OF THE 2022 IFIP/IEEE 30TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) |
Editorial: | IEEE |
Fecha de publicación: | 2022 |
DOI: |
10.1109/VLSI-SoC54400.2022.9939627 |
Notas: | ISI |