Abstract

This paper presents two implementations of a highly-digital time-based sensor-to-digital converter (SDC) targeted for high resolution, low power and ultra-compact circuit footprint. The core structure uses the phase-locked loop (PLL)based architecture, which leads to a highly linear transfer function that enables a simple calibration scheme. The SDCs have been designed using the Skywater 130nm technology and opensource design tools. In the first implementation, the converter has been applied to a capacitive sensor interface application by including the sensor as a capacitive load in a ring oscillator node. The simulated SDC converts capacitive values in a range between 8pF and 8.3pF. Secondly, a novel resistive SDC for temperature measurements between -40 degrees C and 155 degrees C has been implemented in the same technology. The full-system circuit simulation of the resistive SDC shows a SQNR of 12.9ENOB for a 6.2 mu s sampling period and a power consumption of 1.7mW, using only 0.008mm(2) of silicon area.