Abstract

The impact of surface roughness and fractal dimension on the electrical characteristics of sputtered n-CdS/p-Si Schottky diodes were systematically investigated. Atomic force microscopy(AFM) analysis showed that increasing deposition time led to a rise in surface roughness (from 18 to 29 nm) and fractal dimension (from 2.10 to 2.19). Current–voltage(I-V) measurements conducted at room temperature within ±15 V revealed that key diode parameters barrier height(Φ_B), ideality factor (η), and series resistance(Rs) were significantly affected by surface morphology. These parameters were determined using Thermionic Emission Theory, Cheung’s method, and Norde’s model. With increased fractal complexity, ΦB increased from 0.79 to 0.86 eV, η decreased from 3.31 to 3.12, and Rs showed a marked reduction, indicating improved diode performance. The findings underscore the critical role of fractal surface engineering in tuning charge transport and enhancing Schottky diode efficiency for optoelectronic applications.