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Laurent Fesquet

Deputy Director

TIMA Laboratory

Grenoble, Francia

Líneas de Investigación


Microelectronics, Low-Power, Asynchronous Circuit Design, Nonuniform Sampling

Educación

  •  Electrical Engineering, UNIVERSITE DE TOULOUSE. Francia, 1997
  •  Applied Physics, ECOLE NORMALE SUPERIEURE - CACHAN. Francia, 1994
  •  Physics, Ecole Nationale Supérieure de Physique de Strasbourg. Francia, 1993

Experiencia Académica

  •   Associate Professor Full Time

    Grenoble INP, Grenoble Institute of Technology

    Grenoble, Francia

    1999 - A la fecha

  •   Associate Professor Full Time

    TIMA Laboratory

    Grenoble, Francia

    1999 - A la fecha

  •   Chair and Founder Full Time

    French IEEE Solid-State Circuits chapter

    Francia

    2000 - 2014

  •   Co-Chair Full Time

    French IEEE Solid-State Circuits chapter

    Francia

    2015 - A la fecha

  •   Leader of CDSI (Circuits, Devices and System Integration) Group Full Time

    TIMA Laboratory

    Grenoble, Francia

    2007 - A la fecha

  •   Deputy Director Full Time

    TIMA Laboratory

    Grenoble, Francia

    2008 - 2022

  •   Deputy Director Full Time

    TIMA Laboratory

    Grenoble, Francia

    2021 - A la fecha

Experiencia Profesional

  •   Associate Professor Full Time

    Grenoble INP

    Grenoble, Francia

    1999 - A la fecha

  •   Associate Professor Full Time

    TIMA Laboratory

    Grenoble, Francia

    1999 - A la fecha

  •   Leader of CDSI (Circuits, Devices and System Integration) Group Full Time

    TIMA Laboratory

    Grenoble, Chile

    2007 - A la fecha

  •   Deputy Director Full Time

    Centre Interuniversitaire de Microélectronique et des Nanotechnologies (CIME Nanotech)

    Grenoble, Francia

    2008 - 2022

  •   Deputy Director Full Time

    TIMA Laboratory

    Grenoble, Chile

    2021 - A la fecha


 

Article (20)

A dynamical approach to generate chaos in a micromechanical resonator

Defoort, Martial; Rufer, Libor; Basrour, Skandar

Article ISI
MICROSYSTEMS NANOENGINEERING  (2021)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits

Fesque, Laurent; IEEE

Article ISI
2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2019)  (2019)

Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems

Jadue, A. R. Iga; Bastos, R. Possamai; Leite, T. Ferreira de Paiva; Rolloff, O. A.; Diallo, M.; IEEE

Article ISI
2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024  (2018)

Static Timing Analysis of Asynchronous Bundled-Data Circuits

Gimenez, Gregoire; Cogniard, Guillaume; IEEE

Article ISI
2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2019)  (2018)

Method for evaluation of transient-fault detection techniques

Viera, R. A. Camponogara; Dutertre, J. -M.; Maurine, P.; Jadue, R. Iga

Article ISI
MICROELECTRONICS RELIABILITY  (2017)

On-the-fly and Sub-Gate-Delay Resolution TDC based on Self-Timed Ring: A Proof of Concept

El-Hadbi, Assia; Elissati, Oussama; Simatic, Jean; IEEE

Article ISI
2017 IEEE 15TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)  (2017)

Comparison of Low-Voltage Scaling in Synchronous and Asynchronous FD-SOI Circuits

Leite, Thiago Ferreira de Paiva; Bastos, Rodrigo Possamai; Jadue, Rodrigo Iga; IEEE

Article ISI
PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)  (2016)

Adaptive rate filtering a computationally efficient signal processing approach

Qaisar, Saeed Mian; Renaudin, Marc

Article ISI
Signal Processing  (2014)

A Self-timed Ring Based True Random Number Generatora

IEEE

Article ISI
2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2019)  (2013)

A Very High Speed True Random Number Generator with Entropy Assessment

Cherkaoui, Abdelkarim; Fischer, Viktor; Fesquet, Laurent; Aubert, Alain; Bertoni, G; Coron, JS

Article ISI
PROGRESS IN ARTIFICIAL INTELLIGENCE AND PATTERN RECOGNITION, IWAIPR 2018  (2013)

An event-driven FIR filter: design and implementation

Beyrouthy, Taha; IEEE

Article ISI
2011 22ND IEEE INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP)  (2011)

Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs

Zakaria, Hatem

Article ISI
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS  (2011)

IIR digital filtering of non-uniformly sampled signals via state representation

Bidegaray-Fesquet, B.

Article ISI
Signal Processing  (2010)

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling



Article ISI
EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING  (2009)

High-level time-accurate model for the design of self-timed ring oscillators

Hamon, Jeremie; Miscopein, Benoit; IEEE COMPUTER SOC

Article ISI
2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2019)  (2008)

Physical design of FPGA interconnect to prevent information leakage

Chaudhuri, Sumanta; Guilley, Sylvain; Hoogvorst, Philippe; Danger, Jean-Luc; Razafindraibe, Alin; Compton K.; Bouganis, C; Diniz, PC

Article ISI
PROGRESS IN ARTIFICIAL INTELLIGENCE AND PATTERN RECOGNITION, IWAIPR 2018  (2008)

PSL-based Online monitoring of digital systems

Borrione, Dominique; Liu, Miao; Ostier, Pierre; Vachoux, A

Article ISI
APPLICATIONS OF SPECIFICATION AND DESIGN LANGUAGES FOR SOCS  (2006)

Asynchronous level crossing analog to digital converters

Sicard, G

Article ISI
MEASUREMENT  (2005)

FPGA architecture for multi-style asynchronous logic

Huot, N; Dubreuil, H; Wehn, N; Benini, L

Article ISI
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS  (2005)

New class of asynchronous A/D converters based on time quantization

Allier, E; Sicard, G; Fesquet, L; Renaudin, M; Werner B.

Article ISI
2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2019)  (2003)

20
Laurent Fesquet

Deputy Director

TIMA Laboratory

Grenoble, Francia